The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to solder bump structures in the packaging of semiconductor devices.
The packaging of integrated circuit (IC) chips is one of the most important steps in the manufacturing process, contributing significantly to the overall performance, reliability, and cost of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies, such as chip bonding, have become critical. With the continued reduction in device sizes, the density of devices on a chip increases, along with the size of the chip, thereby making chip bonding more challenging. One of the major problems leading to package failure as chip sizes increase is the increasingly difficult problem of coefficient of thermal expansion (CTE) mismatches between materials leading to stress buildup and consequent failure. More specifically, in flip-chip packaging, a series of solder bumps are formed upon a semiconductor substrate in order to facilitate physical and electrical connection of the die to a separate substrate. FIG. 1 is a cross-sectional view of a conventional solder bump structure, which contains the following sub-components:    10 is a semiconductor substrate over which the solder bump is to be formed.    12 is the contact pad, typically containing copper or aluminum, which is to be brought into contact with the solder bump to be formed.    14 is a patterned first passivation layer.    16 is a metal pad layer, typically containing aluminum, which may be input/output routing traces.    18 is a patterned second passivation layer.    20 is a patterned layer of insulation that contains polyimide.    22 is a layer of Under Bump Metallurgy (UBM), and    24 is the formed solder bump.
In advanced IC packaging, the formation of solder bump structures onto the die requires the use of polyimide for planarization in order to facilitate proper attachment of the solder bumps to a separate die. The polyimide layer needs to be applied on the passivation layer in order to planarize the IC surface to resolve the UBM step-coverage problem. More specifically, a layer of polyimide produces a surface in which the step height of underlying features, such as input/output routing traces is reduced, and step slopes are gentle and smooth. It is common in the industry for a polyimide layer to be deposited across the entire semiconductor die following the formation of a passivation layer. However, with the polyimide layer applied globally on the die, chip warpage becomes an issue due to the high coefficient of thermal expansion mismatches between the polyimide layer and the underlying and adjacent structures. A change in the polyimide characteristics may limit the adhesion of the polyimide layer to the underlying passivation layers, as well as to the overlying Under Bump Metallurgy layers thereby leading to device performance and reliability problems, which in turn reduces production yield.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved solder bump structure in advanced IC packaging such as flip chip that avoids the problems associated with conventional solder bump structures.